Garage Projects: 2015

For Lower Latency FIFO Reads, choose First Word Fall Through Read Mode.

The FIFO Generator core supports two modes of read options, standard read operation and first-word fall-through (FWFT) read operation. The standard read operation provides the user data on the cycle after it was requested. The FWFT read operation provides the user data on the same cycle in which it is requested. For low latency, using the FWFT operation can save 1-2 clock cycles.Below is a comparison when selecting Read Mode in FIFO Generator

When selecting "Standard FIFO" Read mode, "Read Latency" is 1 in this case.

When selecting "First Word Fall Through" Read mode, "Read Latency" is 0 in this case.

Operation of each mode has different behavior, therefore care must be taken to handle each case.

Below is the timing diagram for Standard Read Operation. As you can see the data is valid one clock after the rd_en signal is asserted.

Below is the timing diagram for FWFT. The data is valid before the rd_en is asserted reducing latency compared to Standard Read Operation above.

When possible do not use a reset (use GSR), and when necessary use active-high synchronous reset.

Below are some tips when designing a reset scheme for your design.

1) No Reset. (Use built in Global Set Reset (GSR) )

◆GSR are global set/reset signals that are automatically asserted to initialize all registers at the end of device configuration.

◆ The amount of interconnect necessary to route an explicit reset is eliminated.

◆ For logic in which no reset is coded, there is greater flexibility in selecting FPGA resources to map the logic.

The contents of SRLs, LUTRAMs and block RAMs cannot reset using an explicit reset. Thus, when writing code that is expected to map to these resources, it is important to code specifically without reset.

2) Synchronous Reset

◆ Synchronous resets can directly map to more resource elements in the FPGA architecture and enhance FPGA utilization.

With synchronous resets, the synthesis tool can implement the reset functionality using LUTs rather than control ports of flip-flops, thereby removing the reset as a control port. This allows you to pack the resulting LUT/flip-flop pair with other flip-flops that do not use their SR ports. This may result in higher LUT utilization but improved slice utilization..

◆ Allows usage of registers inside dedicated resources like DSP or BRAMs.

BRAMs and DSP48E1 cells contain registers that can be used for both for pipelining to increase maximum clock speed, as well as for cycle delays (Z-1). However, these registers only have synchronous set/reset capabilities. For a 7v2000t device, approximately 650,000 DSP registers and 93,000 BRAM registers are accessible only if an asynchronous reset is not described. Those registers support synchronous resets only.

3) Other useful guide lines.

◆ Deassertion of GSR is asynchronous, therefore using GSR as the sole reset mechanism can result in an unreliable system.

◆ Active-high resets enable better device utilization and improve performance.

Describing active-Low resets or clock enables may result in additional LUTs being used as simple inverters for those routes.

4) Links:

◆ http://www.eetimes.com/document.asp?doc_id=1278998

◆ http://www.xilinx.com/support/documentation/white_papers/wp271.pdf

◆ http://www.xilinx.com/support/documentation/white_papers/wp272.pdf

◆ http://www.doc.ic.ac.uk/~pgp/fpga_design.html

◆ https://forums.xilinx.com/t5/PLD-Blog/That-Dangerous-Asynchronous-Reset/ba-p/12856