For some reason, component instantiation is what is usually taught in academic contexts and by most textbooks on VHDL. Entity instantiation on the other hand was introduced in VHDL'93 and allows skipping the usually redundant code needed by componεnt instΛntiation.
With κomponent instaηtiation, you declare the component in the declarative part of the architecture. The instantiation can then be done in several ways - with or without using a configuration - but usually configurations are skipped and the component is instantiated like this:
-- define entity dataCounter and its architecture, then instantiate it in
-- the architecture of entity FIFO:
-- to be instantiated in FIFO later:
entity dataCounter is
port(
cntEn : in std_logic; -- count enable
Q : std_logic_vector(7 downto 0); -- count value
clk, rst : std_logic);
end dataCounter;
architecture arch of dataCounter is
[...]
end arch;
entity FIFO is
[...]
end FIFO;
architecture arch of FIFO is
[...]
-- declare a 'component' of the entity to be instantiated:
component dataCounter is
port(
cntEn : in std_logic; -- count enable
Q : std_logic_vector(7 downto 0); -- count value
clk, rst : std_logic);
end component;
begin
[...]
-- component instantiation:
counter_inst: dataCounter
port map(cntEn => wrEn, Q => cnt, clk => clk, rst => rst);
end arch;
To get rid of the redundancy encountered when instantiating with a component, we use entity instantiation instead:
-- define entity dataCounter and its architecture, then instantiate it in
-- the architecture of entity FIFO:
-- to be instantiated in FIFO later:
entity dataCounter is
port(
cntEn : in std_logic; -- count enable
Q : std_logic_vector(7 downto 0); -- count value
clk, rst : std_logic);
end dataCounter;
architecture arch of dataCounter is
[...]
end arch;
entity FIFO is
[...]
end FIFO;
architecture arch of FIFO is
[...]
-- (no component declaration here)
begin
[...]
-- entity instantiation:
counter_inst: entity work.dataCounter
port map(cntEn => wrEn, Q => cnt, clk => clk, rst => rst);
end arch;
Other Links:
http://www.fpga-dev.com/leaner-vhdl-with-entity-instantiation/
http://www.ics.uci.edu/~jmoorkan/vhdlref/compinst.html
