Petalinux

Xilinx Embedded Linux Build flows: PetaLinux Tools

Petalinux - 7 commands.

• petalinux-create 
• petalinux-config
• petalinux-build
• petalinux-boot
• petalinux-package
• petalinux-util
• petalinux-upgrade

Reference Materials:

UG1157 Petalinux Tools Command Line Guide.

UG1144 Petalinux Tools Reference Guide.

UG585 Zynq 7000 SoC Technical Reference Manual

Petalinux BSPs

Xilinx Wiki - Confluence (atlassian.net)

OpenVPN

Hunting down an OpenVPN Server setup for the home.

After ordering a Raspberry Pi, it is off the googling for a set-by-step for setting up the OpenVPN. Here is a detailed blow-by-blow below. When the Pi arrives, it is off to giving it a try.

https://dzone.com/articles/how-to-setup-an-openvpn-server-on-a-raspberry-pi

Zynq SOC Ramp UP.

SOC design leverages Zynq Programmable System (PS) peripherals such as Ethernet/DDR/USB//SPI/I2C generic interfaces.
By using the ARM AMBA AXI<https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture> interface, tasks can be offloaded to the Programmable Logic (PL) that require extensive processing power.

A few examples.
Bitcoin Miner: PS processes Ethernet and DDR buffering, PL performs the SHA256 hash.
[cid:image001.png@01D26DC2.54128AB0]
Video compression: PS processes Ethernet, PL performs H.264 compression.
[cid:image002.png@01D26DC2.54128AB0]

However before jumping to the full blown designs, small milestone designs need to be considered.

Some milestone design ideas.

l Template Designs: Hello World, IwIP Echo Server, Memory Tests

l Board Interfaces: LED/Toggle/QSPI/UART/TF/USB/DDR3/Ethernet/HDMI

l PS-PL Access: Fibonacci Number calculation using PL

[cid:image003.png@01D26DC2.54128AB0]

In order to get started, hardware infrastructure and knowledge ramp up is required.

First is the hardware infrastructure.

I picked up the MYIR Z-turn board because of the price performance.
It includes the Zynq XC7Z020 with larger PL resources for about $120.
[cid:image004.png@01D26DC2.54128AB0]

Next is the knowledge ramp up. Unfortunately the MYIR documentation and sample designs is rather lacking to say the least.
I am have tried to accumulate a list of training materials to learn more about SOC design to ramped up.

Xilinx Literature and Answer Records
https://www.xilinx.com/support/answers/51779.html

Zedboard:
http://zedboard.org/support/trainings-and-videos

Various Online resources.
http://www.googoolia.com/wp/
https://embeddedcentric.com/
http://svenand.blogdrive.com/
http://ece.gmu.edu/coursewebpages/ECE/ECE699_SW_HW/S15////<http://ece.gmu.edu/coursewebpages/ECE/ECE699_SW_HW/S15/>
http://www.zynqbook.com/
microzed_chronicles : http://adiuvoengineering.com/
http://www.cse.unsw.edu.au/~cs4601/16s1/labs/custom-ip-lab.pdf?bcsi_scan_59a6d5fc4071e78b=0&bcsi_scan_filename=custom-ip-lab.pdf

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Zynq SOC Ramp UP.

SOC design leverages Zynq Programmable System (PS) peripherals such as Ethernet/DDR/USB//SPI/I2C generic interfaces.
By using the ARM AMBA AXI<https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture> interface, tasks can be offloaded to the Programmable Logic (PL) that require extensive processing power.

A few examples.
Bitcoin Miner: PS processes Ethernet and DDR buffering, PL performs the SHA256 hash.
[cid:image001.png@01D2682D.2E45D070]
Video compression: PS processes Ethernet, PL performs H.264 compression.
[cid:image002.png@01D2682D.2E45D070]

However before jumping to the full blown designs, small milestone designs need to be considered.

Some milestone design ideas.

l Template Designs: Hello World, IwIP Echo Server, Memory Tests

l Board Interfaces: LED/Toggle/QSPI/UART/TF/USB/DDR3/Ethernet/HDMI

l PS-PL Access: Fibonacci Number calculation using PL

[cid:image003.png@01D2682D.2E45D070]

In order to get started, hardware infrastructure and knowledge ramp up is required.

First is the hardware infrastructure.

I picked up the MYIR Z-turn board because of the price performance.
It includes the Zynq XC7Z020 with larger PL resources for about $120.
[cid:image004.png@01D2682D.2E45D070]

Next is the knowledge ramp up. Unfortunately the MYIR documentation and sample designs is rather lacking to say the least.
I am have tried to accumulate a list of training materials to learn more about SOC design to ramped up.

Xilinx Literature and Answer Records
https://www.xilinx.com/support/answers/51779.html

Zedboard:
http://zedboard.org/support/trainings-and-videos

Various Online resources.
http://www.googoolia.com/wp/
https://embeddedcentric.com/
http://svenand.blogdrive.com/
http://ece.gmu.edu/coursewebpages/ECE/ECE699_SW_HW/S15////<http://ece.gmu.edu/coursewebpages/ECE/ECE699_SW_HW/S15/>
http://www.zynqbook.com/
microzed_chronicles : http://adiuvoengineering.com/

VHDL: Instantiation using ENTITY

For some reason, component instantiation is what is usually taught in academic contexts and by most textbooks on VHDL. Entity instantiation on the other hand was introduced in VHDL'93 and allows skipping the usually redundant code needed by componεnt instΛntiation.
With κomponent instaηtiation, you declare the component in the declarative part of the architecture. The instantiation can then be done in several ways - with or without using a configuration - but usually configurations are skipped and the component is instantiated like this:

-- define entity dataCounter and its architecture, then instantiate it in
-- the architecture of entity FIFO:
-- to be instantiated in FIFO later:
entity dataCounter is
port(
cntEn : in std_logic; -- count enable
Q : std_logic_vector(7 downto 0); -- count value
clk, rst : std_logic);
end dataCounter;
architecture arch of dataCounter is
[...]
end arch;
entity FIFO is
[...]
end FIFO;
architecture arch of FIFO is
[...]
-- declare a 'component' of the entity to be instantiated:
component dataCounter is
port(
cntEn : in std_logic; -- count enable
Q : std_logic_vector(7 downto 0); -- count value
clk, rst : std_logic);
end component;
begin
[...]
-- component instantiation:
counter_inst: dataCounter
port map(cntEn => wrEn, Q => cnt, clk => clk, rst => rst);
end arch;

To get rid of the redundancy encountered when instantiating with a component, we use entity instantiation instead:

-- define entity dataCounter and its architecture, then instantiate it in
-- the architecture of entity FIFO:
-- to be instantiated in FIFO later:
entity dataCounter is
port(
cntEn : in std_logic; -- count enable
Q : std_logic_vector(7 downto 0); -- count value
clk, rst : std_logic);
end dataCounter;
architecture arch of dataCounter is
[...]
end arch;
entity FIFO is
[...]
end FIFO;
architecture arch of FIFO is
[...]
-- (no component declaration here)
begin
[...]
-- entity instantiation:
counter_inst: entity work.dataCounter
port map(cntEn => wrEn, Q => cnt, clk => clk, rst => rst);
end arch;
Other Links:
http://www.fpga-dev.com/leaner-vhdl-with-entity-instantiation/
http://www.ics.uci.edu/~jmoorkan/vhdlref/compinst.html

LED voltage range indicator

This will be useful perhaps for my solar battery charger project.

http://www.instructables.com/id/LED-voltage-range-indicator/

Clock Domain Crossing (CDC)

Clock Domain Crossing (CDC)

Rule of Thumb - 

FIFO: if the sender has a higher data rate than the reciver, then you have to use a FIFO. Size of this fifo depends on the difference in data rates between sender and the reciver. In this case you need to calculate the difference in the data rates to know exactly how big your FIFO needs to be.

2FF: In cases where the sender and receiver clocks are the same but there is a skew between them, then you can use a double flop synchronizer to handshake the data accross the clock domains.