FPGA.GP.01.04.ML506

After trying out different coregen adders, the dsp48 adder as used to try and fit a design in the ml506 board. The ml506 uses a virtex-5 sx50t device that has 288 dsp48`s. The adders were instantiated as below and the sha256 transform LOOP_LOG2 parameter what set to 2.

wire [31:0] t1, t2, new_w, t3, t4;
wire cout0, cout1, cout2;
wire gnd = 0;

dsp48_32bit_adder adder0 (.a(rx_state[`IDX(7)]),.b(e1_w),.c_in(gnd),.c_out(cout0) );
dsp48_32bit_adder adder1 (.a(ch_w),.b(rx_w[31:0]),.c_in(cout0),.c_out(cout1) );
dsp48_32bit_adder adder2 (.a(k),.b(gnd),.c_in(cout1),.s(t1) );
dsp48_32bit_adder adder3 (.a(e0_w),.b( maj_w),.c_in(gnd),.s(t2) );
dsp48_32bit_adder adder4 (.a(s1_w),.b(rx_w[319:288]),.c_in(gnd),.c_out(cout2) );
dsp48_32bit_adder adder5 (.a(s0_w),.b(rx_w[31:0]),.c_in(cout2),.s(new_w) );
dsp48_32bit_adder adder6 (.a(rx_state[`IDX(3)]),.b(t1),.c_in(gnd),.s(t3) );
dsp48_32bit_adder adder7 (.a(t1),.b(t2),.c_in(gnd),.s(t4) );

Below is a Map Report snippet that summarizes the resources required for this build.

Design Summary
--------------
Slice Logic Utilization:
  Number of Slice Registers:                26,148 out of  32,640   80%
  Number of Slice LUTs:                     31,944 out of  32,640   97%
    Number of fully used LUT-FF pairs:      25,863 out of  32,229   80%
Slice Logic Distribution:
  Number of occupied Slices:                 8,099 out of   8,160   99%
Specific Feature Utilization:
  Number of DSP48Es:                           256 out of     288   88%

By using 88% of the dsp48`s, the design was able to fit into the sx50t device. The number of LUTS is almost max at 97%, however the percent of fully used LUT/FF pairs is only at 80%. This is probably because the FF is only 80%, thus reporting the same for fully used pairs also. This might hint that the design does not have much more potential for resource savings.

This will be the baseline to start characterizing the hashrate. A similar approach will be performed using the ml505, however since there are only a handful of dsp48, it is not expected to be able to pack the same design. Probable need to dial down the sha256 transform LOOP_LOG2 parameter down to 3 perhaps.