VHDL: Instantiation using ENTITY

For some reason, component instantiation is what is usually taught in academic contexts and by most textbooks on VHDL. Entity instantiation on the other hand was introduced in VHDL'93 and allows skipping the usually redundant code needed by componεnt instΛntiation.
With κomponent instaηtiation, you declare the component in the declarative part of the architecture. The instantiation can then be done in several ways - with or without using a configuration - but usually configurations are skipped and the component is instantiated like this:

-- define entity dataCounter and its architecture, then instantiate it in
-- the architecture of entity FIFO:
-- to be instantiated in FIFO later:
entity dataCounter is
port(
cntEn : in std_logic; -- count enable
Q : std_logic_vector(7 downto 0); -- count value
clk, rst : std_logic);
end dataCounter;
architecture arch of dataCounter is
[...]
end arch;
entity FIFO is
[...]
end FIFO;
architecture arch of FIFO is
[...]
-- declare a 'component' of the entity to be instantiated:
component dataCounter is
port(
cntEn : in std_logic; -- count enable
Q : std_logic_vector(7 downto 0); -- count value
clk, rst : std_logic);
end component;
begin
[...]
-- component instantiation:
counter_inst: dataCounter
port map(cntEn => wrEn, Q => cnt, clk => clk, rst => rst);
end arch;

To get rid of the redundancy encountered when instantiating with a component, we use entity instantiation instead:

-- define entity dataCounter and its architecture, then instantiate it in
-- the architecture of entity FIFO:
-- to be instantiated in FIFO later:
entity dataCounter is
port(
cntEn : in std_logic; -- count enable
Q : std_logic_vector(7 downto 0); -- count value
clk, rst : std_logic);
end dataCounter;
architecture arch of dataCounter is
[...]
end arch;
entity FIFO is
[...]
end FIFO;
architecture arch of FIFO is
[...]
-- (no component declaration here)
begin
[...]
-- entity instantiation:
counter_inst: entity work.dataCounter
port map(cntEn => wrEn, Q => cnt, clk => clk, rst => rst);
end arch;
Other Links:
http://www.fpga-dev.com/leaner-vhdl-with-entity-instantiation/
http://www.ics.uci.edu/~jmoorkan/vhdlref/compinst.html

LED voltage range indicator

This will be useful perhaps for my solar battery charger project.

http://www.instructables.com/id/LED-voltage-range-indicator/

Clock Domain Crossing (CDC)

Clock Domain Crossing (CDC)

Rule of Thumb - 

FIFO: if the sender has a higher data rate than the reciver, then you have to use a FIFO. Size of this fifo depends on the difference in data rates between sender and the reciver. In this case you need to calculate the difference in the data rates to know exactly how big your FIFO needs to be.

2FF: In cases where the sender and receiver clocks are the same but there is a skew between them, then you can use a double flop synchronizer to handshake the data accross the clock domains.

Xilinx Vivado Supported OS

I am thinking trying different Linux Distros and would like to know what OS is supported by Xilinx Tools.

Below is a result of my search. The list is documented in UG973 (v2015.1) April 1, 2015.

From this result, I am currently running Ubuntu on my machines at home and RedHat at work.

Custom firmware for home router

I little bit straying away from FPGA`s, but network related none the less.

I have been looking for cost reduction of mobile phone, hardline phone and home internet.

Currently I estimate I will pay 9000 joy for mobile phone and 5000 joy for home internet and imp phone, totaling 14,000 joy per month. Ridiculous.

Recently SIM Free phones have become available, so I am going to drop my mobile phone and internet and replace it with 3 SIM Free IC`s, one for my mobile phone and the others for Pocket Wi-Fi.

The problem with Pocket Wi-Fi is that the range is limited and requires a workaround.

I can work around by using my old Buffalo Air station g54 set it up in bridge mode to rebroadcast my Pocket Wi-Fi signal.

However I need to flash it with third-party firmware because this router only support WPS and requires the original signal to source from another Buffalo router.

It seems that are 3 big firmware solutions for this project; DD-WRT, Tomato and Openwork.

http://www.lifehacker.com.au/2015/04/how-to-choose-the-best-firmware-to-supercharge-your-wi-fi-router/

I decided to use DD-WRT firmware. Below are some links to set up my router. Wish me luck!

How to Extend Your Wi-Fi Network With an Old Router

http://lifehacker.com/how-to-extend-your-wi-fi-network-with-an-old-router-915783308/963787201

An in-depth DD-WRT guide to walk you through the process of DD-WRT custom firmware on your router

http://lifehacker.com/how-to-supercharge-your-router-with-dd-wrt-508138224

some more useful blogs about upgrading the firmware, however in japanese

best for installation of firmware -> http://otti-website.com/?p=82
more about installation procedure -> http://hirokikana.blogspot.jp/2008/09/wbr-g54dd-wrt.html
stories about successes and failures -> http://ankosan.jp/dd-wrt-upgrade.html

and a very nice procedure to set up the router as a repeater using dd-wrt
http://www.wi-fiplanet.com/tutorials/article.php/3655041/DD-WRT-Tutorial-5-Wireless-Repeater.htm

Cascading FIFOs to Increase Depth and Width

I have been having trouble using the fifo generator to create large depth fifos.

Simulation and bitstream was successful, however the actual hardware did not function successfully.

After doing a search on the Xilinx website, I located a recommended way to cascade fifos as below.

http://www.xilinx.com/support/answers/58928.html

In the same answer record, width can be expanded as below.

FPGA.GP.Packet Encapsulation

High level packet info. Writing packet parsers and packet generators, it is easy to get emersed in the details. Lets step back and review conceptually.

Also when asked in an interview, "what is Ethernet", this might help answer those questions.

One way to look at a tcp/ip packet is encapsulation using the OSI reference layers

Each layer of the packet is peeled back until the application receives the data from the bottom up.

                     [tcp payload]  - Layer 5 - Application

                [tcp [tcp payload]] - Layer 4 - Transport

         [ip    [ip       payload]] - Layer 3 - Network

[ethernet[ethernet        payload]] - Layer 2 - Data Link

wire                                - Layer 1 – Physical

[]

A couple of nice diagrams of an encapsulated packet.

Here is an even more detailed diagram of a layered packet with all the header content detials.

Explanation of each OSI Layer:

http://www.tcpipguide.com/free/t_OSIReferenceModelLayerSummary.htm

FPGA.GP.Choosing Memory Type for FIFO Generation

When creating FIFO using the FIFO Generator, below is a guideline to selecting memory types.

For example, for deep depth message buffering, choose Block RAM.

Benchmarking suggests that the advantages the Built-In FIFO implementations have over the block RAM FIFOs (for example, logic resources) diminish as external logic is added to implement features not native to the macro. This is especially true as the depth of the implemented FIFO increases. It is strongly recommended that users requiring features not available in the Built-In FIFOs implement their design using block RAM FIFOs.

FIFO Generator v13.0, page 11

PG057 November 18, 2015