Cascading FIFOs to Increase Depth and Width

I have been having trouble using the fifo generator to create large depth fifos.

Simulation and bitstream was successful, however the actual hardware did not function successfully.

After doing a search on the Xilinx website, I located a recommended way to cascade fifos as below.

http://www.xilinx.com/support/answers/58928.html

In the same answer record, width can be expanded as below.