By using the ARM AMBA AXI<https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture> interface, tasks can be offloaded to the Programmable Logic (PL) that require extensive processing power.
A few examples.
Bitcoin Miner: PS processes Ethernet and DDR buffering, PL performs the SHA256 hash.
[cid:image001.png@01D2682D.2E45D070]
Video compression: PS processes Ethernet, PL performs H.264 compression.
[cid:image002.png@01D2682D.2E45D070]
However before jumping to the full blown designs, small milestone designs need to be considered.
Some milestone design ideas.
l Template Designs: Hello World, IwIP Echo Server, Memory Tests
l Board Interfaces: LED/Toggle/QSPI/UART/TF/USB/DDR3/Ethernet/HDMI
l PS-PL Access: Fibonacci Number calculation using PL
[cid:image003.png@01D2682D.2E45D070]
In order to get started, hardware infrastructure and knowledge ramp up is required.
First is the hardware infrastructure.
I picked up the MYIR Z-turn board because of the price performance.
It includes the Zynq XC7Z020 with larger PL resources for about $120.
[cid:image004.png@01D2682D.2E45D070]
Next is the knowledge ramp up. Unfortunately the MYIR documentation and sample designs is rather lacking to say the least.
I am have tried to accumulate a list of training materials to learn more about SOC design to ramped up.
Xilinx Literature and Answer Records
https://www.xilinx.com/support/answers/51779.html
Zedboard:
http://zedboard.org/support/trainings-and-videos
Various Online resources.
http://www.googoolia.com/wp/
https://embeddedcentric.com/
http://svenand.blogdrive.com/
http://ece.gmu.edu/coursewebpages/ECE/ECE699_SW_HW/S15////<http://ece.gmu.edu/coursewebpages/ECE/ECE699_SW_HW/S15/>
http://www.zynqbook.com/
microzed_chronicles : http://adiuvoengineering.com/
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